Author Topic: Bug in 0.9.11.1  (Read 1600 times)

ChillyWilly

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Bug in 0.9.11.1
« on: June 25, 2012, 05:34:52 AM »
I found a bug in the 8 Mbit DRAM cart handling... the code currently does like this for read/write:

Code: [Select]
static u8 FASTCALL DRAM8MBITCs0ReadByte(u32 addr)
{
   addr &= 0x1FFFFFF;

   switch (addr >> 20)
   {
      case 0x04: // Dram area
         return T1ReadByte(CartridgeArea->dram, addr & 0x7FFFF);
      case 0x06: // Dram area
         return T1ReadByte(CartridgeArea->dram, 0x80000 | (addr & 0x7FFFF));
      default:   // The rest doesn't matter
         break;
   }

   return 0xFF;
}

which is wrong as it only handles the first mirror of the bank. It needs to handle the second and third as well like real hardware, like this:

Code: [Select]
static u8 FASTCALL DRAM8MBITCs0ReadByte(u32 addr)
{
   addr &= 0x1FFFFFF;

   switch (addr >> 20)
   {
      case 0x04: // Dram area
      case 0x05:
         return T1ReadByte(CartridgeArea->dram, addr & 0x7FFFF);
      case 0x06: // Dram area
      case 0x07:
         return T1ReadByte(CartridgeArea->dram, 0x80000 | (addr & 0x7FFFF));
      default:   // The rest doesn't matter
         break;
   }

   return 0xFF;
}

All six functions need patching.